Semiconductors and integrated circuit chips have become ubiquitous within many products due to their continually decreasing cost and size. Miniaturization in general allows increased performance (more processing per clock cycle and less heat generated) at lower power levels and lower cost. Present technology is at or approaching atomic-level scaling of certain micro-devices such as logic gates, FETs, capacitors, etc. Circuit chips with hundreds of millions of such devices are not uncommon. Further size reductions appear to be approaching the physical limit of trace lines and micro-devices that are embedded upon and within their semiconductor substrates. The present invention is directed to such micro-sized FET devices. A FET is a transistor consisting of a source, a gate, and a drain. The action of the FET depends on the flow of majority carriers along a channel between the source and drain that runs past the gate. Current through the channel, which is between the source and drain, is controlled by the transverse electric field under the gate. More than one gate may be used to more effectively control the channel. The length of the gate determines how fast the FET switches and how fast the circuit can operate, and is generally about the same as the length of the channel (i.e., the distance between the source and drain). State of the art gate lengths are today on the order of 50 nm, and are moving toward 10 nm within the next decade. Such size reductions should enable upwards of a billion devices on a single chip. However, such small scaling necessitates greater control over performance issues such as short channel effects, punch-through, and MOS leakage current.
Recently, the size of FETs has been successfully reduced through the use of one or more fin-shaped channels, known as fins. FETs employing fins are known as FinFETs. Previously, complementary metal-oxide semiconductor (CMOS) devices were substantially planar along the surface of the semiconductor substrate, the exception being the FET gate that was disposed over the top of the channel. Fins break from that paradigm by using a vertical structure in order to maximize surface area of the channel that is exposed to the gate. The gate controls the channel more strongly because it extends over three sides of the fin shaped channel, rather than only across the top of a more traditional planar channel. An example of a FinFET is shown in FIG. 1, which is a TEM micrograph of a prior art FET with six fins. Each pair of fins comprises an NFET and a PFET.
One method to enhance fin performance is to fabricate fins in layers of disparate materials. One such exemplary device assigned to the assignee of this invention is described in U.S. Pat. No. 6,252,284 B1, “Planarized Silicon Fin Device”, which is directed to controlling short-channel effects.
Often, one of the layers of a multi-layered planarized FET fin is strained silicon. It has been previously discovered that biaxially stretching the crystalline lattice structure of silicon can speed the flow of electrons through a transistor, thereby enhancing performance and decreasing power consumption. There is a natural tendency of atoms in layers of disparate materials to align with one another by stretching and/or compressing their mismatched lattice structures along a planar interface of the mismatch. Varying the respective thickness and chemical composition of the materials aids in controlling the extent of extension and compression in either material. As an example, FIG. 2a depicts a silicon lattice structure and a germanium lattice structure, not to scale, in their natural (unstretched) states. When silicon is disposed (or grown) on a thicker layer of germanium, as in the SiGe compound of FIG. 2b, the lattice of silicon stretches while the lattice of germanium remains substantially unchanged, resulting in strained silicon.
This result is achieved as the comparatively greater thickness of the germanium layer yields greater structural integrity and greater resistance to lattice compression. The actual process of lattice stretching may also, or alternatively, entail atoms of Si and Ge intermixed within a lattice structure. This integrates both atoms within a single layer, wherein the larger Ge atoms force the integrated lattice structure to stretch, as compared to a natural (unstretched) silicon lattice structure. The opposite effect from that shown in FIG. 2b can also be realized, wherein a thinner layer of germanium exhibits lattice compression when bonded to a thicker layer of silicon. Strained silicon has been shown to enhance electron/hole mobility by up to 70% in NFETs, and up to 30% in PFETs. Other materials such as silicon germanium carbon may be used to form the crystalline heterojunction that enhances conductivity. There are several methods used to form strained layers, including chemical vapor deposition (CVD) and molecular beam epitaxy (MBE).
Strained silicon disposed along a plane has been used in prior art FinFETs. However, current leakage continues to be a limiting factor in further scaling of FETs toward the atomic limit. Current leakage becomes an ascendant concern as miniaturization progresses because shorter length FET gates, which generally track the channel length, have less ability to control electric charge carriers (holes or electrons).
The unintentional flow of charge carriers when the transistor is off is termed “current leakage.” Current leakage is the primary source of power consumed by an idle transistor. Current leakage may be classified into two types: MOS off current, wherein an unintended current passes through the channel despite the gate attempting to shut off current completely; and gate tunneling leakage current, wherein unintended current follows a parasitic pathway flowing into the channel, diffusions, or silicon body. As FET channel lengths continue to decrease, it is expected that gate tunneling leakage current will become a predominant concern for designers. The fin structure enhances gate control over the channel, but gate control over current is not absolute, even in prior art FinFETs. Compounding the current leakage problem, miniaturization enables ever-lower power levels that require more absolute gate control. Current leakage that escapes the gate's control is less distinguishable from intentional current, particularly at low current levels.
What is needed is a FET that allows small scaling with enhanced performance for both NFETs and PFETs. Preferably, the FET should improve gate control in a fin structure that exhibits enhanced carrier transport properties.